Stereo signal monitoring

ABSTRACT

To monitor stereo audio signals associated with a TV video signal, the two stereo audio channels are converted to digital form (20, 21), a memory (22) has bits written into it at addresses formed by successive pairs of such values in digital form to form a map therein of a Lissajou figure representing the relationship between the two channels, the memory is read out linearly in synchronism with the operation of the monitor, and the output inserted into the TV video signal (VID) being displayed. The memory may be read out diagonally, so as to produce a diamond display, by a line counter (LB, RB) and a bit counter (LL, RL) for each channel, the line counters being loaded with predetermined counts at the beginning of each field and counting lines and the bit counters being loaded from the line counters at the beginning of each line and counting bits along the lines, three of the counters (LL, RL, RB) counting in one direction and the fourth (RL) in the other. The counters (LL, LB, RL, RB) are larger than the memory, the excess portion of the counts being used to control (via 45, 52) the enabling of the memory read-out. ACG (automatic volume control) and graticule generation may be provided.

BACKGROUND OF THE INVENTION

The present invention relates to the monitoring of stereo audio signalsassociated with TV video signals.

In broadcasting generally, and in television broadcasting in particular,the provision of stereo sound is becoming commonplace. This posesspecial problems in the production and monitoring of TV programmes. Itis difficult to monitor sound quality adequately by ear, particularlyunder production conditions, and some form of instrumentation whichgives an indication of sound amplitude and phase is desirable. Inparticular, it is desirable to be able to monitor the relationshipbetween the two channels of a stereo audio signal.

A well-known technique for doing this is to provide a separate monitorconsisting of a conventional oscilloscope which has the two channels ofthe stereo signal fed to its X and Y inputs respectively; the resultingdisplay is a Lissajou figure. However, this arrangement has thedisadvantage that it is separate from the display of the associated TVpicture on a TV monitor. The operator therefore has to make an activeeffort to check the oscilloscope, and there is also ample opportunityfor error in associating the oscilloscope display with the appropriateone of a large number of monitors in a typical array of TV monitors.

A stereo audio monitor has also been developed which uses a TV-typepicture raster display instead of an oscilloscope vector-type display,with the Lissajou figure being synthesized from the two audio signals asa TV-type video signal. This, however, suffers from the samedisadvantages as the oscilloscope display.

SUMMARY OF THE INVENTION

The main object of the present invention is to provide means formonitoring stereo audio signals associated with a TV video signal whichalleviates or overcomes these problems. Subsidiary objectives are toachieve convenience and simplicity.

Accordingly the present invention provides an audio signal monitoringsystem for stereo audio signals associated with a TV video signal,comprising means for converting the two channels of a stereo audiosignal to digital form and writing successive pairs of values into amemory to form a map therein of a Lissajou figure representing therelationship between the two channels, and means for reading out thememory linearly in synchronism with the operation of a TV monitor andinserting the output into the TV video signal being displayed on themonitor.

Preferably the memory is read out diagonally so as to produce a diamonddisplay on the monitor in which identical signals on the two audiochannels are represented by a vertical line.

The read-out means preferably comprise a line counter and a bit counterfor each channel, the line counters being loaded with predeterminedcounts at the beginning of each field and counting lines and the bitcounters being loaded from the line counters at the beginning of eachline and counting bits along the lines, three of the counters countingin one direction and the fourth in the other. Preferably the countersare larger than the memory, the excess high order portion of the countsbeing used to control the enabling of the memory read-out. Preferablyalso there is a display location selection memory containing one or morepairs of prestored counts any pair of which can be selected for loadinginto the line counters.

The system may include means for generating a graticule on the diamonddisplay. Such means may comprise either logic circuitry fed from thecounters or a second memory operated in parallel with the first memory.

The means for inserting the memory output into the TV signal maycomprise pulse stretching means, adder means, and gating means. Thegating means are preferably controlled partially or wholly by the excessportion of the counts. The insertion means may include means for eithersuperimposing the Lissajou figure on the video picture on the TV monitoror means for generating a uniform background to the Lissajou figure inthe diamond. The insertion means may also include means for insertingthe graticule at a different brightness to that of the Lissajou figure.

The system may include automatic gain control means for controlling thesize of the Lissajou figure. Such means may comprise a counter which iscaused to count up or down depending on whether the magnitude of theinput audio signal is greater or less than the count, the counting ratepreferably being larger if the count is low than if it is high, and thecount preferably being held above some minimum signal value.Alternatively the counter may count down gradually if the count is high,and be reset immediately to the magnitude of the input audio signal ifthe count is low. The counter preferably feeds a digital-to-analogconverter which provides a reference voltage to the analog-to-digitalconverters.

The circuitry of the system may be accommodated substantially completelyon a printed circuit board which plugs into the monitor. The controlsare preferably readily accessible e.g. by being made available at thefront of the monitor, or by being on a self contained control unitcoupled to the board by a wire or infra-red links.

An audio signal monitoring system embodying the invention will now bedescribed, by way of example, with reference to the drawings, in which:

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a composite drawing showing various forms of display which canbe generated by the system;

FIGS. 2A and 2B together are a block diagram of the system;

FIGS. 3 to 5 are diagrams illustrating the operation of the system; and

FIG. 6 is a block diagram of a modification of a part of FIG. 2A.

DESCRIPTION OF THE INVENTION

FIG. 1 shows the face 10 of a TV monitor, which will normally have a TVpicture (here shown as a tricolour flag on a flagpole) displayed on it.The present system operates to superimpose any one of the five audiosignal displays 11 to 15 on the picture. (All five possible displays areshown on the same drawing for conciseness and to illustrate therelationship between them.) If the large display is selected, then thisdisplay 11 is presented as a Lissajou figure drawn as a white line overthe main picture but not otherwise obscuring it. (This is shown innegative form in the drawing, i.e. as a black line.) If a small displayis selected, then one of the displays 12 to 15 is presented as aLissajou figure drawn as a white line on a black background, obscuring apart of the main picture. The small display can be located in any cornerof the main picture, as shown.

The display is generated as a Lissajou figure in a diamond-shaped field,i.e. a square field skewed at an angle of 45°, as shown. The two audiochannels drive the display parallel to the +45° and -45° directions. Thelarge display 11 shows the Lissajou figure for a typical stereo audiosignal in which the two channels are in the proper relationship. Display12 shows the same situation in which the signals in the two channels areidentical; the Lissajou figure becomes a vertical straight line,produced by two identical signals. Display 13 shows the effect of thetotal loss of the right-hand channel; the Lissajou figure becomes astraight line pointing to the left, produced by only the left-handchannel signal. Display 14 shows the effect of a phase reversal in onechannel; the Lissajou figure is a horizontal line. Display 15 shows theeffect of a DC bias or offset in one of the channels; the Lissajoufigure is a vertical straight line which is displaced from the centre ofthe diamond in a direction parallel to one pair of edges of the diamond.Other faults also generally produce distinctive effects; for example, aphase shift in one channel will spread out the Lissajou figure from aline to an ellipse. Combinations of faults will generally producecombinations of the individual effects.

FIGS. 2A and 2B are a block diagram of the circuitry of the system. Thetwo audio channels, left audio LA and right audio RA, feed a pair ofanalog-to-digital converters 20 and 21, which produce 8-bit signalswhich are fed to a memory 22. This memory is a 64 Kbit static RAM, whichacts as a 256×256×1 bit memory. A clock unit 23 includes a free-running20 MHz oscillator the output of which is divided down by 3 to producethree sequential signals CW (write), CR (read), and CE (erase) each at6.7 MHz. (Obviously the erase signals would not be required if a dynamicRAM were used instead). The CW signal is used to clock the A/Dconverters 20 and 21, and their outputs are fed to the address inputs tothe memory 22 to write a 1 bit into the selected address (also clockedby the CW clock signal). Thus the Lissajou figure is mapped into thememory 22 bit by bit along the line of the figure as it is generated.

The "raw" video signal to the monitor, carrying the TV picture to bedisplayed, is fed as signal VID IN to a pulse insertion unit 24, wherethe selected display (11, 12, 13, 14, or 15) is inserted in it, toproduce the combined video signal VID OUT which is used to modulate theCRT of the monitor. The signal VID IN is also fed to a sync pulseextractor 25, which extracts the line pulses LP and field pulses FP tocontrol the operation of the system.

The system also includes memory read addressing circuitry, showngenerally at 26, the purpose of which is to read out the contents of thememory 22. This read-out is arranged to take place bit by bit alongsuccessive diagonal lines through the memory 22; each diagonal line isread out during the appropriate part of a scan line of the monitor, andthe read-out steps on from one diagonal to the next as the TV scan stepson from one line to the next. It will be realized that this diagonalscanning of the memory 22 results in its contents being mapped onto themonitor display as a skewed square or diamond, as shown in FIG. 1. Eachbit is read out from the memory 22 on the clock pulse CR, and is passedto the pulse insertion unit 24; each bit read-out is followed by itserasure from the memory on the following CE clock pulse. The memory readcircuitry changes state on the CW clock pulses.

An AGC circuit 27 is fed by the outputs of the A/D converters 20 and 21and controls their sensitivity, so that the Lissajou figure is enlargedif the audio level is low.

The A/D converters 20 and 21 each produce an 8-bit output, with the zeropoint of the analog input being at the middle of the digital range. Thatis, the digital output corresponding to and input audio signal voltagelevel of 0 V is 7 F or 80 (hexadecimal); digital outputs of 00 and FFcorrespond to peak negative and positive inputs respectively. Thisensures correct location of the Lissajou figure in the memory 22 and thedisplay 11, 12, 13, 14, or 15.

The memory read addressing circuitry 26 comprises a pair of counters, aline counter and a bit counter, for each channel; that is, a linecounter LL and a bit counter BL for the L channel and a line counter LRand a bit counter BR for the R channel. The line counters are loadedwith predetermined counts at the start of each field, thesepredetermined counts determining the position of the display, and countthe line pulses LP. Each bit counter is loaded with the contents of thecorresponding line counter at the start of each line, and counts theclock pulses CW. Three of the counters count in the same direction,while the fourth counts in the opposite direction.

FIG. 3 shows the fine detail of the counter operation. Three successivescan lines SC1 to SC3 of the monitor are shown, with the counts of theleft and right line counters LL and RL shown to the left of the startsof the line scans. For illustrative purposes, it is assumed that theline counters' counts are 255 for both the counters for the first linescan shown; both these counters count down for successive line scans.The counts of the left bit counter LB are shown above each line andthose of the right bit counter RB shown below the line. As shown, thesecounters are set to the counts in the line counters at the beginning ofeach line scan; thereafter, these counters count the CW clock pulses asthe line scan progresses. The LB counter counts down, while the RBcounter counts up. Corresponding counts of counter LB form a pattern ofdiagonal lines L in one direction and corresponding counts of counter RBform a pattern of diagonal lines R in the other direction, as shown.

FIG. 4 is a similar diagram on a smaller scale, showing the relationshipbetween the L and R count lines and the scan lines. Each pair of bitcounter counts, an LB count and an RB count, corresponds to the read-outof the bit in the corresponding address in the memory 22. Comparing thebit counter count pattern of FIG. 4 with the address ordering shown inFIG. 1, it is evident that the bit pattern in the memory as shown inFIG. 1 is mapped onto the monitor with an anticlockwise rotation of 45°,giving a diamond pattern as required. The clock frequency of the CWclock pulses is chosen so that the diamond is approximately square.

It is apparent from FIG. 4 that only half the bits in the memory 22 areutilized; those whose L and R addresses in the memory 22 have oppositeparities are not read out. This means that the effective size of thememory 22 is only 32 Kbits. The remaining 32 Kbits will be written intobut will never be read out.

If the clock frequency is doubled and the clock pulses are directed tothe two counters alternately, so that they count alternately instead ofsimultaneously, all bits in the memory 22 can be utilized. In practice,however, this refinement results in an improvement which is relativelymarginal in view of the fact that the present system is primarilyintended to give qualitative rather than quantitative information.

It will also be seen that no distinction is made between successivefields. Because successive fields are interlaced but the read-out isidentical for all fields, this means that the display oscillates up anddown by one line on the two successive fields of a frame. This minoroscillation does not cause any significant flickering or irritation tothe user, and is therefore accepted. (The Lissajou figure will alsonormally change on each successive field, making the oscillationnormally undetectable). It will however be realized that by a slightelaboration of the arrangements for setting the counters at thebeginning of each field, the 32 Kbits not read out on one field can beread out on the next field, thus using the whole of the memory 22 andachieving interlace. (For perfect interlace, the counter clocking mustalso be delayed by half a clock period on alternate fields.)

It will be clear that the location of the diamond pattern on the screendepends on where the start point (counts of 255 in both counters) is,and this depends on the presetting of the counts in the line counters atthe start of each frame.

As described so far, the diamond is generated with a height of 256 linesand a width of 256 dots. Its physical width is therefore determined bythe number of dots in a line. A line scan (in a 50 Hz, 625-line system)takes 64 μs (of which 12 μs is used for flyback), and a dot time is 0.17μs, i.e. the reciprocal of the 20 MHz frequency of the clock unit 23.This gives a roughly square diamond.

To generate the smaller patterns 12 to 15, the size of the memory iseffectively reduced by a linear factor of 4. This is achieved byeffectively stepping the counts of the bit counters LB and RB on by 4'sinstead of 1's. This in turn is achieved by providing multiplexers inthe outputs of the bit counters, one set of inputs being fed with thefull 8 bit count outputs and the other set being fed with the bottom 6bits transposed up by 2 bits (and the bottom 2 bits being forced to 0).The effective size of the memory 22 is thus 2 Kbits for any of the smallpatterns 12 to 15.

The full memory size of 64 Kbits is continually being written into bythe signals from the A/D converters 20 and 21, but only the active 2Kbits are read out for a small display. Of course, if the large display11 is selected after a small display has been running for some time, thefirst field of the large display will read out the accumulation of 1bits in the extra 30 Kbits of the active 32 Kbits of locations used forthe large display. However, it will take only a single field for theselocations to be cleared, and this transient effect can be ignored.(However, if it is desired to suppress this effect, the display can beblanked for the first frame following the change of size).

Also, as described so far, the addressing of the memory 22 will cycleeach time a bit counter reaches 0 and restarts at 255. This would resultin a repeated pattern of diamonds covering the whole of the monitor. Toensure that only one diamond is displayed, the counters are extended byan additional 4 high order bits, and the high order bits are decoded andmemory read-out is enabled only for high-order values of 0 in both bitcounters. In effect, the bit counters generate an extended pattern of16×16 diamonds as shown fragmentarily in FIG. 5, in which each diamondof the extended pattern is labelled with the two hexadecimal values ofthe top 4 bits of the two bit counters (in the order LR). Thus diamond00 is selected, and the other 255 diamonds of the extended pattern arenot displayed. The extended pattern is large enough that the monitorscreen occupies less than half its width and height even if smalldiamonds are being generated, and the presetting of the line counterscan thus locate the pattern at any desired location on the screen.

Referring again to FIGS. 2A and 2B, a display select memory DS MEM 30has permanently stored in it the starting counts for the LL and RLcounters. There are 10 such pairs of counts stored in it, 5 for the 5displays for the 625-line standard and 5 for the corresponding displaysfor the 525-line standard. By choosing suitable values for these storedcounts, the displays can be located at any desired locations on themonitor screen. A switchable selection unit 31 selects the appropriatepair of counts; this unit may be controlled by switches on the monitoror by a remote control unit connected to the monitor by either a wirelink or an infra-red link.

These counts are permanently supplied to the two line counters LL andRL. The load control inputs LD of these counters are fed with the fieldpulses FP, which loads them with these counts at the start of eachfield. The count inputs CT- (both these counters counting down) of thesecounters are fed with the line pulses LP. These line pulses are also fedto the load control inputs LD of the two bit counters LB and RB, whichare also fed with the contents of the LL and RL counters respectivelyfor loading. The count inputs of the bit counters LB and RB are CT- andCT+ respectively (these two counters counting down and up respectively)and are fed with the CW pulses from the clock 23. All four of thesecounters are 12-bit counters.

The output of the bit counter LB is split into the lower 10 bits and theupper 2 bits. These two outputs are fed to one set of correspondinginputs of a multiplexer 32, and the lower 10 bits are transposed up by 2bits to the top 10 bits of the other set of inputs of the multiplexer,the bottom 2 bits of this set being fed with 00. The bottom 8 bits ofthe output of this multiplexer are fed to a set of AND gates 33 whichfeed the L address bus 34 of the memory 22. The gates 33 are enabled byan OR gate 35 which is fed with the CR and CW clock pulses from clock23. The L bus 34 is also fed from the A/D converter 20 via a set of ANDgates 36 which are enabled by the CW clock pulses from clock 23. Thusthe bus 34 is fed from the A/D converter 20 for writing a bit of theLissajou figure, and from the counter LB for reading a bit and thenerasing it.

The right-hand channel is treated similarly, with counter RB feeding amultiplexer 37 which feeds the address bus 38 via a set of AND gates 39.A/D converter 21 feeds the bus 39 via a set of AND gates 40.

The A/D converters and the bit multiplexers may of course be tristatedevices effectively incorporating the AND gates which they are shown asfeeding.

The top 4 bits of from each of the multiplexers 32 and 37 are fed to aNOR gate 45, which produces a 1 only when all bits fed to it are 0, i.e.when the bit counters LB and RB are selecting a point in the diamond 00in the extended pattern shown in FIG. 5. This output is fed to an ANDgate 46, which is interposed between the OR gate 35 and the gates 33 and39, to allow the bit counts to be fed to the memory 22 only for theselected diamond. The output of the memory 22, i.e. the sequence of bitsread out from it, is fed to a resettable one-shot 47 which stretches thepulses to a length which will be observable on the monitor. Thestretched pulses are fed to an adder circuit 48, which is also fed withthe incoming video signal, and produces the video output signal VID OUT.The bits read out from the memory 22 are inserted into the video signalas pulses at (or slightly below) the full white level.

The raw video signal VID IN is fed to the adder circuit 48 via an analoggate circuit 49. This gate is disabled by the pulses from the one-shot47, which are fed to its control input via an inverter 50 and an ANDgate 51. Thus the video signal is prevented from reaching the addercircuit 48 when a pulse is being inserted; this prevents the videosignal VID OUT from exceeding the full white level. (Obviously, alimiter operating at the full white level could be used instead.) Ifdesired, a 1 (or a continuous sequence of 1's) from the memory 22 canhave black level pulses inserted before and/or after the white levelsignal corresponding to those bits, to give greater emphasis to theLissajou figure.

The selection unit 31 produces an output on a line SML when any one ofthe small displays 12 to 15 is selected. This signal is fed to themultiplexers 32 and 37, to select the upwardly transposed counts fromthe bit counters LB and RB. This signal is also fed to a NAND gate 52,which is also fed by gate 45, and which feeds the AND gate 51. When theLissajou figure is being displayed, i.e. the bit counters have countswithin the diamond 00, NOR gate 45 produces a 1; when also one of thesmall displays has been selected, signal SML will also be 1 and theoutput of gate 52 will be 0. This will disable the analog gate 49 (viathe AND gate 51) for the whole of the time that the Lissajou figure isbeing displayed. The raw video signal is thus prevented from reachingVID OUT, and the background for the diamond of any of the small displaysis therefore black. (For the large display, the output of NAND gate 52is 1, and the Lissajou figure of the large display is thereforesuperimposed on the main video picture.)

If desired, the output of the one-shot 47 may also feed a colour controlcircuit (not shown) which sets the colour of the inserted pulses formingthe Lissajou figure to a desired colour, e.g. green.

If desired, a frame or graticule can also be generated in the diamonddisplay. This requires the generation of pulses on particularcombinations of counts from the bit counters LB and RB. The resultinggraticule pulses are then inserted into the video signal in the same wayas the Lissajou figure pulses from the memory 22. The graticule pulsesmay conveniently be inserted as grey level signals.

Graticule pulses can be generated in two ways. One way is to detect theparticular combinations of counts from the bit counters LB and RB bymeans of logic circuitry. This can readily be used to generate an outerframe for the display and lines in the display parallel to the outerframe; by using adders and subtractors, lines diagonal to theframe--i.e., lines which are horizontal and vertical--can also begenerated. The other way is to use a second memory, like the memory 22,which has the graticule permanently stored in it. This second memorywould be addressed by the same buses 34 and 38 as the memory 22.

The automatic gain control (AGC) circuit or compander(compressor-expander) circuit 27 includes a counter 55 the count ofwhich is converted to analog form by a D/A converter 56, the output ofwhich is fed to the A/D converters 20 and 21 to act as their referencevoltage. The higher the count of counter 55, the higher the referencevoltage, and the greater the conversion range of the converters 20 and21. Since the converters 20 and 21 have the same reference voltage, thecharacteristics of the two audio channel conversions will be identical.The counter 55 is caused to count up relatively rapidly if the audiosignal level rises above that corresponding to its count, and to countdown relatively slowly if the audio signal strength falls below thecorresponding count. This ensures that the system responds rapidly to arise in audio signal level.

The strength of the audio signal is measured crudely by combining thetwo digital audio signals from the converters 20 and 21. Considering theL signal, this is processed by a logic circuit 57. The top bit of thedigital L signal represents the sign of the corresponding analog signalL. If this bit is 1, the remaining 7 bits of the digital L signal arefed through a set of 7 AND gates 58 enabled by the top bit. If this bitis 0, it enables a second set of 7 AND gates 59 via an inverter 60, andthis set of gates 59 is fed with the bottom 7 bits of the digital Lsignal via a set of 7 inverters 61. The CR signal is processed by asimilar logic circuit 62.

The two 7-bit outputs of each of the logic circuits 57 and 62 are fed toa set of 7 OR gates 63. The output of these OR gates is therefore abitwise combination of the magnitudes of the L and R audio signals,having a 1 in each position for which either of the L and R signals hasa 1 (after conversion if the signal happens to be negative). A fixed 1is fed to the 3rd bit position of the set of OR gates 63, preventingtheir output from falling below a lower limit.

The output of the gates 63 is fed to a comparator 64, which is also fedwith the output of the counter 55. If the counter output is less thanthe output of the gates 63, the comparator enables a gate 65; if thecounter output is greater than the output of gates 63, it enables a gate66. The clock signal CW is fed through two divide circuits 67 and 68 insequence, to generate clock signals at reduced rates. The output of thefirst divide circuit 67 is fed to gate 65, and that of the second togate 66. Gate 65 feeds the + (up) count input of counter 55, and gate 66feeds its - (down) count input.

The count of counter 55 therefore follows the magnitude of the audioinput signals, at a limited rate and subject to a lower count limit. Ifthe audio signal magnitude exceeds the count of counter 55, then thecount is increased relatively rapidly, whereas if the audio signalmagnitude is less than the count, the count decreases relatively slowly.

Of course, switchable control means can be provided for disabling thecircuitry feeding the counter 55 and forcing its count to the maximum ifdesired.

FIG. 6 shows an alternative form of AGC circuit. The signals from theanalog-to-digital converters 20 and 21 undergo several stages ofprocessing in this circuit. First, the signals are converted from signedto absolute values; then the larger of the two absolute values isselected; then the counter 79 is set immediately to the selected valueif its count is below the selected value but counts slowly downotherwise; and finally the count in the counter is decoded to give areference level for the converters 20 and 21.

The A/D converter 20 produces an 8-bit output, as noted above, with theextreme positive value of input (analog) signal corresponding to 11111111, the extreme negative to 0000 0000, and zero to 1000 0000 or 01111111. Thus the top bit (the left-hand bit in these representations)indicated the sign of the analog signal. The remaining 7 bits of theoutput of converter 20 are fed to a set of 7 equivalence gates 75 whichare also all fed with the top bit. Hence if the analog signal ispositive, the 7 low bits are fed through the 7 equivalence gatesunchanged, and the 7-bit value corresponds directly to the value of theinput signal (i.e. 000 0000 corresponds to zero, and 111 1111 topositive peak). If the analog signal is negative, the value of the 7bits from converter 20 runs from 111 1111 (zero) to 000 0000 (peaknegative); since the top bit is 0, the 7 equivalence gates 75 convertthese 7-bit values to the range 000 0000 (zero) to 111 1111 (peaknegative).

Hence the gate set 75 converts the 8-bit signed value from converter 20to a 7 bit absolute amplitude. A similar set of 7 equivalence gates 76,each fed with a corresponding one of the 7 low-order bits from converter21 and all fed with the top bit from that converter, produce theabsolute value of the signal from that converter.

The two absolute values from the gate sets 75 and 76 are fed to acomparator 77 and to a multiplexer 78. The output of the comparator 77indicates which of the two (7-bit) signals fed to it is the larger, andcontrols the multiplexer to select that larger value.

A counter 79 has a CT- (count down) input fed with the clock signals WCvia a divider 80. Its count therefore tends to decrease slowly butregularly. The output of this counter is fed to a comparator 81, whichis also fed with the output of the multiplexer 78, and the output ofthis comparator is fed to the load enable input LE of the counter 79.The output of the multiplexer is fed to the load input L of thiscounter. If the count of the counter falls below the output of themultiplexer, the load input is enabled and the output of multiplexer isimmediately loaded into the counter. The count of the counter thereforedecreases gradually for as long as the absolute value of the larger ofthe signals from the converters 20 and 21 exceeds that count, but isimmediately forced up to that value the moment that value rises abovethe count in the counter.

The output of the counter 79 is also fed to a digital-to-analogconverter 82, the output of which is passed through an adjustablescaling circuit 83 to an analog buffer circuit 84 the output of which isfed to the analog-to-digital converters 20 to 21 as their scalingreference level.

An effective lower limit can be set for the count of the counter 79 byvarious means. One of the lower order bits from the multiplexer 78 canbe forced to 1. (If this is done, that bit and any bits of still lowerorder are irrelevant for the AGC circuitry and their circuits can beomitted, reducing the number of bits processed by the AGC circuitry.)Alternatively, the input to the digital-to-analog converter 82 can havea low-order part with at least a leading 1 added below the bits from thecounter 79. (Again, the AGC circuitry may ignore some of thelowest-order bits from the converters 20 and 21.)

A switch SW allows selection between the varying reference level fromscaling circuit 83 and a fixed level from a second adjustable scalingcircuit 85, which is preferably set so that the saturation level of theconverters 20 and 21 is the peak nominal audio signal level. With thescaling circuit 85 selected, any excursion of the audio signal beyondthe peak nominal level is readily recognizable, since the Lissajoufigure reaches and runs along the edge of the diamond in which it isdisplayed.

It is possible to detect such saturation or its imminence and cause adistinctive colouration of the Lissajou figure. Saturation occurs wheneither of the 8-bit signals from the converters is either hex 00 or FF;an upper byte of hex 0 or F may be taken as indicating its imminence.Such colouration may be either the whole of the Lissajou figure or justthe saturated part, and the hue may if desired be made dependent on thedegree of saturation and/or whether the saturation is of the left,right, or both channels.

It is obvious that several different audio stereo signals can bemonitored on a single monitor by providing a separate monitoring systemfor each signal. Also, two unrelated audio signals (e.g. signals in twodifferent languages) can be fed to the present system, which would thengive a simple indication of whether both signals are present or one orother (or both) are absent.

I claim:
 1. Apparatus for monitoring stereo audio signals associatedwith a TV video signal by generating a Lissajou figure, said apparatuscomprising:analog-to-digital converter means (20, 21) for converting thetwo channels of the stereo audio signal to instantaneous values indigital form, a first memory (22) into which bits are written ataddresses formed by successive pairs of said instantaneous values indigital form to form a map therein of a display of a Lissajou figurerepresenting the relationship between the two channels, read-out means(26) for reading out the first memory linearly in synchronism with theoperation of a monitor (10), and insertion means (24) for inserting thememory output into the TV video signal (VID IN), wherein the readoutmeans (26) read the first memory out diagonally, so as to produce adiamond display on monitor (10).
 2. Apparatus according to claim 1characterised in that the read-out means comprise a line counter (LL,RL) and a bit counter (LB, RB) for each channel, the line counters beingloaded with predetermined counts at the beginning of each field andcounting lines and the bit counters being loaded from the line countersat the beginning of each line and counting bits along the lines, threeof the counters (LL, RL, RB) counting in one direction and the fourth(RL) in the other.
 3. Apparatus according to claim 2 characterised inthat the capacity of the counters (LL, LB, RL, RB) is larger than thesize of the first memory, the excess high-order portion of the countsbeing used to control (via 45, 52) the enabling of the first memoryread-out.
 4. Apparatus according to claim 3 characterised by a displaylocation selection memory (30) containing one or more pairs of prestoredcounts which can be selected for loading into the line counters (LL,RL).
 5. Apparatus according to claim 1 characterised by a graticulemeans for generating a graticule on the display.
 6. Apparatus accordingto claim 5 characterised in that the graticule means comprise logiccircuitry driven by the circuitry which reads out the first memory. 7.Apparatus according to claim 5 characterised in that the graticule meanscomprise a second memory which is read out in parallel with the firstmemory.
 8. Apparatus according to claim 3 characterised in that theinsertion means comprise pulse stretching means (47) fed from theread-out means, adder means (48) fed from the pulse stretching means,and gating means (49) fed from the pulse stretching means and feedingthe adder means.
 9. Apparatus according to claim 3 characterised in thatgating means (49) are controlled partially or wholly by the excessportion of the counts.
 10. Apparatus according to claim 9 characterisedin that the insertion means include means (45, 52, 51) operable eitherto superimpose the Lissajou figure on the video picture on the TVmonitor or to generate a uniform background to the Lissajou figure. 11.Apparatus according to claim 6 characterised in that the insertion meansincludes means for inserting the graticule at a different brightness tothat of the Lissajou figure.
 12. Apparatus according to claim 1characterised by AGC (automatic gain control) means for controlling thesize of the Lissajou figure).
 13. Apparatus according to claim 12characterised in that the AGC means comprise a digital-to-analogconverter (56; 82) which provides a reference voltage to theanalog-to-digital converter means (20, 21).
 14. Apparatus according toclaim 12 characterised in that the AGC means comprise a counter (55; 79)which is caused to count up or down depending on whether a magnitude ofan input audio signal is greater or less than the count.
 15. Apparatusaccording to claim 14 characterised by means (64-67) causing a countingrate of the counter to be larger if the count is low than if it is high.16. Apparatus according to claim 14 characterised by means (80, 81)causing the counter to count down gradually if the count is high, and bereset immediately to the magnitude of the input audio signal if thecount is low.
 17. Apparatus according to claim 14 characterised by meansfor holding the count of the counter (55; 79) above a minimum signal 18.Apparatus according to claim 8 wherein said gating means are controlledpartially or wholly by the excess portion of the counts.
 19. Apparatusaccording to claim 5 wherein said insertion means includes means forinserting the graticule at a different brightness to that of theLissajou figure.